1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device prepared by forming an insulating layer on a semiconductor substrate by an ion implantation technique and semiconductor elements or semiconductor integrated circuits are formed by using at least one of the semiconductor layers isolated by the insulating layer.
2. Description of the Prior Art
Various methods have been proposed to decrease the isolation area between semiconductor elements and the junction capacitance and to completely isolate the semiconductor elements of a semiconductor integrated circuit for the purpose of increasing the degree of integration of the circuit, operation speed and reliability. As disclosed in U.S. Pat. No. 3,855,009, for example, a semiconductor device is prepared by implanting ions of oxygen or nitrogen into a monocrystalline silicon wafer, annealing the wafer to form an insulating layer consisting of a compound of the implanted ions and silicon, epitaxially depositing silicon on the insulating layer, and forming a semiconductor element or a semiconductor integrated circuit on the epitaxial silicon layer.
However, when using such a method, it is difficult to obtain semiconductor devices having desired characteristics for the following reasons:
Firstly, since ions of oxygen, for example, are directly implanted into the semiconductor substrate at the time of ion implantation, the surface of the substrate is contaminated by carbon contained in the space through which the ion beam passes. The origin of such carbon is the mist of diffusion oil used in a diffusion pump. For this reason, when the epitaxial silicon layer is formed after annealing the substrate, such lattice defects as dislocation and stacking faults will be formed when the degree of contamination is high. Furthermore, when an MOS transistor is formed by diffusing an impurity directly into a silicon wafer formed with an insulating layer, the contaminated surface directly affects the characteristics of the MOS transistor. Accordingly, in the semiconductor device prepared by the method disclosed in the above U.S. patent, it is necessary to etch the surface of the substrate after the annealing step.
Secondly, in the semiconductor device prepared using the above patented method, since the thermal expansion coefficient of the region of the insulating layer formed by implanting ions in a cooling step subsequent to annealing differs greatly from that of the silicon substrate, strain is induced in the silicon substrate thereby tending to bend it. Where a silicon oxide layer is formed as the insulating layer by implanting oxygen ions, the thermal expansion coefficient 0.48.times.10.sup.-6 per degree C. of the SiO.sub.2 layer is about 1/10 of the 4.68.times.10.sup.-6 per degree C. coefficient of the silicon wafer. When oxygen ions were implanted into a 3-inch silicon wafer having a thickness of 350 microns with an implantation energy of 150 KeV, and a dose of 1.2.times.10.sup.18 atoms/cm.sup.2, and then annealed at a temperature of 1150.degree. C. for two hours, the silicon wafer was flexed 38 microns. When the silicon wafer flexes in this manner, crystal defects and cracks are formed in the surface layer of the silicon wafer due to strain. Consequently, when an epitaxial silicon layer is formed directly on the silicon wafer or an impurity is directly diffused into the silicon wafer, the crystal defects and cracks cause problems similar to those caused by the contamination of the surface. Furthermore, as such crystal defects and cracks reach considerable depths relative to the wafer surface, such defects cannot be eliminated completely even when the wafer surface is etched after annealing as taught by the above-mentioned U.S. patent.